1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device including a silicon oxide film (which film will be sometimes referred to hereafter as an “FSG film”) containing fluorine (F), which film serves as an inter-layer insulation film or the like, and more particularly to a method of manufacturing a semiconductor device in which an FSG film is formed by a CVD (chemical vapor deposition) process.
2. Description of the Related Art
Recently, among low-dielectric constant materials which are required as films between layers of metal wiring, FSG films formed by a plasma CVD process have attracted attention. Of these low-dielectric constant materials, FSG films formed by the plasma CVD process undergo relatively little degasification, and are stable films. Moreover, these FSG films have excellent characteristics with regard to filling in of narrow slits.
A process flow for a conventional semiconductor device is shown in FIGS. 10A to 10H.
A metal lamination film 13 is formed by a sputtering process on an insulating layer 12, which is formed on a substrate 11 which includes an unillustrated transistor (FIG. 10A). At the metal lamination film 13, for example, an aluminium alloy 13a and a high melting point metal 13b are layered. Patterning is carried out at this metal lamination film 13, and metal wiring 14 is formed (FIG. 10B). Then, an FSG film 15 of, for example, 1000 nm is formed on the metal wiring 14 and the exposed insulating layer 12 by, for example, a plasma CVD process (FIG. 10C). Thereafter, a surface of the FSG film 15 is levelled by a CMP (chemical and mechanical polishing) process. To suppress the release of fluorine (F) at this time (that is, to prevent fluorine degasification), a silicon-rich film of silicon oxide of, for example, 200 nm is formed to serve as a cap film 16 by, for example, a plasma CVD process (FIG. 10D). Then, through-holes 17 are opened through the FSG film 15 and the cap film 16 (FIG. 10E). After this, a TiN film 18 of, for example, 50 nm is formed on the cap film 16 and hole portions at the through-holes 17 by a sputtering process or CVD process (FIG. 10F). Thereafter, a W (tungsten) film 19 is formed by a CVD process so as to completely fill in the through-holes 17 (FIG. 10G). Finally, the TiN film 18 and the W film 19 are removed by a CMP process except at portions corresponding to the through-holes 17 (FIG. 10H). These steps are repeated a desired number of times, and then heat treatment is performed at around 400° C. in an atmosphere including, for example, H2. Damage is repaired, the first wiring 14 (an aluminium alloy film) is stabilized, and thus a semiconductor device with a multi-layer wiring structure is completed.
However, it has been found that degasification of a portion of the fluorine included in the FSG film occurs, and this fluorine is released. Thus, for example, peeling of the cap film from the FSG film and the like, leading to detachment of wiring peripheries, may occur. Some of this fluorine may be trapped due to the formation of the cap film. However, in the recent semiconductor devices, as the number or layers becomes greater, the total thickness of FSG films increases and the number of heat treatments increases, fluorine degasification cannot be completely prevented, and film peeling at peripheries of the wiring occurs. Furthermore, if the cap film is made thinner, then the effects of fluorine trapping is reduced due to the thinning of the film, when the W film is removed by the CMP process. If the cap film is made thicker, there are problems with an increase of inter-layer volume, etching accuracy and the like. Therefore, it is required that fluorine degasification be suppressed at the FSG film itself and/or that the effect of fluorine trapping by the cap film be enhanced.